A read stability and a write performance of memory cells within a semiconductor memory device have a tradeoff relationship. Recently, due to the increased integration density of the semiconductor memory device, inconsistencies in electrical characteristics, particularly threshold values, of transistors forming the memory cells have increased to an extent which is no longer negligible. Because of the above inconsistencies in the threshold values, it is becoming increasingly difficult to simultaneously achieve the desired read stability and the desired write performance of the memory cells. The read stability improves by setting the threshold values of the transistors forming the memory cells to a high value, but the write performance is deteriorated thereby.
In general, the read stability improves when a potential of a word line in the semiconductor memory device is decreased, but the write performance consequently deteriorates. In the conventional semiconductor memory device, the read stability and the write performance can be simultaneously achieved even when the potential of the word line is set to a power supply voltage when this word line is selected. However, due to the above described increase in the inconsistencies caused by the increased integration density of the semiconductor memory device, it is becoming more difficult to simultaneously achieve the read stability and the write performance. Hence, a method has been proposed in which the word line potential at the time of reading is set lower than the power supply voltage in order to improve the read stability, and the word line potential at the time of writing is set higher than that at the time of reading in order to prevent deterioration of the write performance. According to this proposed method, the threshold values of the transistors forming the memory cells are set in the same manner as in the case of the conventional semiconductor memory device, and the threshold values are not set to a particularly high value.
FIG. 1 is a circuit diagram illustrating a first example of a conventional semiconductor memory device. A semiconductor memory device 1-1 illustrated in FIG. 1 includes a memory cell array 11, a word line driver circuit 12, a column selection circuit 13, and a write and read circuit (hereinafter simply referred to as a write/read circuit) 14. Each memory cell MC within the memory cell array 11 is connected to a word line WL and bit lines BL and /BL. In this example, the semiconductor memory device 1-1 forms a static random access memory (SRAM). In the memory cell array 11, a row is selected by selecting the word line WL, and a column is selected by selecting the bit line pair BL and /BL. One bit line BL and a bit line /BL forming a pair with this one bit line BL are supplied with mutually inverted signals when selected. In FIG. 1, RSS denotes a row selection signal, CSS denotes a column selection signal, WRSS denotes a write and read switching signal (hereinafter simply referred to as a write/read switching signal), and DB denotes a data bus. For example, if the memory cell array 11 amounts to 1 kilo-words (Kwords), the memory cells MC amounting to {(128 rows)*(4 columns)}*{4 bytes (=32 bits)} are provided, where 1*11 denotes a multiplication.
A description will be given of a case where the potential of the word line WL is changed between the time of writing and the time of reading in the semiconductor memory device 1-1 having the structure illustrated in FIG. 1. If the potential of the word line WL at the time of writing is set higher than that at the time of reading, the memory cells MC in each column in which the word line WL is selected but the bit line pair BL and /BL is not selected assume a state similar to a reading state, and there is a possibility that data held by the memory cells MC in the state similar to the reading state will be destroyed.
On the other hand, depending on the structure of the semiconductor memory device 1-1, the writing and the reading are performed for every byte that is connected to the same word line WL. In such a structure, there is a possibility that the required potential of the word line WL will be different depending on the memory cells MC, even among the memory cells MC connected to the same word line WL.
Hence, a semiconductor memory device having a structure described in a Japanese Laid-Open Patent Publication No. 2003-16786 has been proposed. FIG. 2 is a circuit diagram illustrating a second example of the conventional semiconductor memory device. In FIG. 2, those parts which are substantially the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. A semiconductor memory device 1-2 illustrated in FIG. 2 has a structure corresponding to that proposed in the Japanese Laid-Open Patent Publication No. 2003-16786. In the semiconductor memory device, a voltage variable word line driver circuit 12A is provided in place of the word line driver circuit 12 illustrated in FIG. 1. By connecting a different word line WL for each column, it is possible to avoid generation of a memory cell MC for which the column is not selected even though the word line WL is selected within a memory cell array 11A. In addition, the word line WL is set to a potential suitable for the writing at the time of writing and to a potential suitable for the reading at the time of reading. In the semiconductor memory device 1-2, identical (or corresponding) columns are grouped into blocks, and each block is driven by a separate word line WL.
However, according to the semiconductor memory device 1-2 illustrated in FIG. 2, the wiring length of the data bus DB to which the bit line pair BL and /BL is connected becomes extremely long because the identical columns are grouped into the blocks, and the operation speed of the semiconductor memory device 1-2 greatly deteriorates. For this reason, the structure of the semiconductor memory device 1-2 is unsuited for a cache SRAM for use in high-end processors which particularly require high-speed operation.
In order to compensate for the deterioration of the operation speed of the semiconductor memory device 1-2, it is conceivable to provide a sense amplifier for each bit line pair BL and /BL. But in this case, an area occupied by the sense amplifier is not negligible since a large number of sense amplifiers will be provided, which goes against the demands to increase the integration density of the semiconductor memory device 1-2.
In addition, in the semiconductor memory device 1-2, an area occupied by the data bus DB increases, and the number of write/read circuits 14A provided for each byte also increases. Moreover, in the production process of the memory cell array 11A, characteristic deteriorations and pattern (or shape) defects of the memory cells MC are generated due to discontinuities occurring at exposure and processing stages, and for this reason, it is necessary to provide dummy cells in a periphery of functioning cells which actually function in a normal manner. When the memory cell array 11A is segmented for each byte, the number of dummy cells to be provided on the outer periphery of the memory cells MC which are used as the functioning cells, in order to compensate for the characteristic deteriorations and the pattern defects, will amount to the number of segments, which goes against the demands to increase the integration density of the semiconductor memory device 1-2.
According to the conventional semiconductor memory device, there was a problem in that it is difficult to improve the read stability and the write performance, without greatly interfering with the demands to increase the integration density of the semiconductor memory device.